1. Field of the Invention
This invention relates to electronic circuits and particularly to a low level clamping circuit for stabilizing current flow through a circuit node connected to a high level voltage clamping network. The invention is particularly applicable to programmable logic arrays.
2. Description of the Prior Art
In a digital logic network such as a programmable logic array, a plurality of word lines are connected to a plurality of bit lines through logic gates. The product terms of the logic gates are delivered to the bit lines, which are connected by OR gates to sense amplifiers. Because all the output sense nodes are virtually independent of each other, significant variations in their output voltage levels may occur in ordinary operation.
To eliminate unwanted swings in the levels of the bit lines, it is a common design practice to provide a linear tracking, constant voltage column clamp which is diode connected to all the bit lines. The column clamp establishes a generally constant high level voltage for the sense nodes, and prevents radical excursions of the sense node voltages. Therefore, the sense amplifiers are provided with a constant high level reference voltage basis for reducing the digital signal swings of the product terms.
The state-of-the-art column clamp circuit, however, introduces into the logic array its own inherent deficiencies and limitations. For example, in a large programmable logic array, there may be 64 product terms, each presented at an individual sense node. The product terms are mutually independent so that any one or all of the bit lines may be on at a given time. When most or all of the bit lines are off, a large current load is sunk to ground through the column clamp. Conversely, actuation of many or all of the bit lines will shunt the current load to ground through the word lines, and the column clamp will experience a sudden load drop. This load drop, which is a function of the programming of the logic device, will cause the voltage of the sense nodes to drop briefly but precipitously. The column clamp circuit is intended to prevent such fluctuations, but in reality its response is undesirably slow in responding to large load shifts.
During large load changes, the diode connections of the sense nodes to the column clamp act to defeat the intended purpose of the column clamp. That is, the 64 diodes each exert an intrinsic capacitance, and the aggregate of these capacitances creates a significant RC network connected to the reference node of the column clamp. The column clamp may require two or three nanoseconds to overcome the resulting RC rise time effect, which in a system having a 10 nanosecond access time, is, of course, quite significant. While the column clamp voltage is rising to return to its preset value, the sense node high level reference node voltage drop indicative of a logic level shift may fall below the noise margin of the sense amplifiers, causing the sense amplifiers to switch prematurely, or to read incorrect bit line conditions. This condition causes a glitch in which the system fails to operate. Thus, to minimize access time and increase the speed of the logic device, it is desirable to prevent such voltage excursions in the column clamp network.